The present invention relates generally to memory storage devices and, more particularly, to a design structure for implementing power savings during addressing of Dynamic Random Access Memory (DRAM) devices.
DRAM integrated circuit arrays have been existence for several years, with their dramatic increase in storage capacity having been achieved through advances in semiconductor fabrication technology and circuit design technology. Considerable advances in these two technologies have also resulted in higher and higher levels of integration that permit dramatic reductions in memory array size and cost, as well as increased process yield.
A DRAM memory cell typically includes, as basic components, an access transistor (switch) and a capacitor for storing a binary data bit in the form of a charge. Typically, a first voltage is stored on the capacitor to represent a logic HIGH or binary “1” value (e.g., VDD), while a second voltage on the storage capacitor represents a logic LOW or binary “0” value (e.g., ground). A basic drawback of a DRAM device is that the charge on the capacitor eventually leaks away and therefore provisions must be made to “refresh” the capacitor charge, otherwise the data bit stored by the memory cell is lost.
As power demands increase in computer systems, new ways to save power are constantly in demand. Recent studies have shown that in a memory cache, up to 95% of all memory access can occur in only 25% of the cache. This results in a large number of memory devices that are constantly “at the ready,” and thus drawing power. In present DRAM architectures, it is generally desirable from a performance standpoint to have deep (large) page accesses for certain types of applications. However, addressing large page sizes can result in row address commands applied to many devices within the DRAM array, which is a large consumer of active power in a memory system. FIG. 1 depicts an exemplary DRAM architecture 100, which illustrates that the activation of row devices results in a relatively large consumption of power.
In the simplified example shown, the DRAM architecture 100 of FIG. 1 is an array of 4 by 4 cells 102, each including one storage capacitor 104 and one access transistor 106 (however, modern DRAM devices may be thousands of cells in length/width). During a read operation, the row of the selected cell is activated, turning on each of the transistors coupled to the word line 108 of the row and connecting the capacitors of that row to the associated sense lines 110. The sense lines 110 are in turn (selectively) coupled to sense amplifiers 112, which distinguish and latch signals that represent a stored 0 or 1. The amplified value from the appropriate column is then selected and connected to the output. At the end of a read cycle, the row values are restored to the capacitors 104, which were discharged during the read. A write operation is implemented by activating the row and connecting the data values to be written to the sense lines 110, which charges the cell capacitors 104 to the desired values. During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in.
In some applications, it is possible to “step” the accesses through a row, effectively optimizing the power that was spent in activating the entire row. However, in many applications, the random nature of accesses can offset the benefits of page depth, as the system never uses the large page accesses, or is not able to “step” through enough columns to make up for the number of row devices which were initially powered. Thus, methods for reducing the power related to actively addressing data in a memory system are generally desirable.
One approach to reducing power consumption relates to placing DRAMs into a “degrade” mode, wherein the DRAM enters a deactivated, stand-by state. Additional information in this regard may be found in U.S. Patent Application publication US 2006/0047493 by Gooding. In particular, the '493 publication introduces the use of deep power down modes of real memory portions within a plurality of volatile real memory portions without loss of data.
In view of the above, it would be desirable to be able to continue to allow access to the DRAM while also conserving power, and in a manner that does not result in additional time taken to bring the DRAM out of a dormant stand-by mode.